The present invention relates to a semiconductor device provided with semiconductor elements and to a method for the fabrication of such a semiconductor device. The present invention relates more particularly to a semiconductor device protecting its semiconductor elements and securing establishment of electrical connections between the semiconductor elements and external equipment.
In recent years, since electronic equipment is becoming smaller and smaller in size and being highly improved in function, there have been strong demands for improvement in packaging density as well as the miniaturization and the high operation rate of the semiconductor device. In order to meet these demands, various forms of packaging have been developed. For example, the COC (Chip On Chip) module has been developed as a packaging form (Japanese Unexamined Patent Gazette No. H10-32307).
Hereinafter, a semiconductor device of a conventional COC module (hereinafter referred to as the xe2x80x9cCOCxe2x80x9d) and a method for the fabrication of such a COC will be described with reference to FIG. 5.
FIG. 5 schematically shows a cross section of the conventional COC 100. The COC 100 includes a first semiconductor chip 101 containing a first semiconductor integrated circuit part and a second semiconductor chip 102 containing a second semiconductor integrated circuit part. These first and second semiconductor chips 101 and 102 are electrically connected together by a face-down technique. Since the face-down technique is used, the major surface of the semiconductor chip 102 faces downward while the backside surface of the semiconductor chip 102 faces upward.
The first semiconductor chip 101 is mounted on a die pad 106a of a lead frame 106, and the second semiconductor chip 102, located above the first semiconductor chip 101, is smaller in chip size than the first semiconductor chip 101. Both the first semiconductor chip 101 and the second semiconductor chip 102 are encapsulated with an encapsulating resin 108.
Formed on the major surface of the first semiconductor chip 101 are a plurality of first element electrodes 103 electrically connected to the first semiconductor integrated circuit part. On the other hand, formed on the major surface of the second semiconductor chip 102 are a plurality of second element electrodes 104 electrically connected to the second semiconductor integrated circuit part. The first semiconductor chip 101 and the second semiconductor chip 102 are placed such that their major surfaces face each other, and a portion 103a of the first element electrodes 103 of the first semiconductor chip 101 and the second element electrodes 104 of the second semiconductor chip 102 are connected together electrically by a connection member (for example, a bump) 105. Further, a portion 103b of the first element electrodes 103 of the first semiconductor chip 101 is electrically connected to an external lead (an external electrode) 106b of the lead frame 106 by a boding wire (for example, a wire of Au).
Referring still to FIG. 5, a method for the fabrication of the conventional COC 100 will be described below.
First, the first semiconductor chip 101 and the second semiconductor chip 102 are prepared. Following this, the connection member 105, made of solder or the like, is formed on each of the second element electrodes 104 of the second semiconductor chip 102. Next, the second semiconductor chip 102 is mounted onto the first semiconductor chip 101 such that each of the second element electrodes 104 of the second semiconductor chip 102 is connected to each of the first element electrode portions 103a of the first semiconductor chip 101 through the connection member 105. Then, the connection member 105 is melted, thereby electrically connecting together the second element electrodes 104 of the second semiconductor chip 102 and the first element electrode portions 103a of the first semiconductor chip 101.
Next, the first semiconductor chip 101 is mounted onto the die pad 106a of the lead frame 106. This is followed by wire bonding of electrically connecting together the first element electrode portion 103b of the first semiconductor chip 101 and the external lead 106b of the lead frame 106 by a bonding wire (for example, a wire of Au). Lastly, the fist semiconductor chip 101, the second semiconductor chip 102, the die pad 106a of the lead frame 106, and a portion of the external lead 106b of the lead frame 106 are all encapsulated by the encapsulating resin 108, and the COC 100 is obtained.
However, the conventional COC 100 has difficulties in being multipin-ized to a further extent. That is, in the COC 100, external connection is established by the external lead 106b extracted from a lateral surface of the encapsulating resin (the package) 108, which makes it difficult to further provide many external electrodes (external terminals). Furthermore, the external dimensions of the COC 100 are constrained by the package dimensions such as the size of the lead frame 106. Therefore, it is difficult to reduce the size of the COC 100.
Bearing in mind the above-described problems, the present invention was made. Accordingly, a major object of the present invention is to provide a semiconductor device capable of coping with multipin-ization and reducible in size and a method for the fabrication of such a semiconductor device.
The present invention provides, in order to achieve the aforesaid object, a semiconductor device which comprises (a) a first semiconductor element having a major surface on which a plurality of first element electrodes are disposed, (b) a second semiconductor element having a major surface on which a plurality of second element electrodes are disposed, the major surface of the second semiconductor element facing the major surface of the first semiconductor element, (c) a connection member electrically connecting together at least a portion of the plural first element electrodes of the first semiconductor element and at least a portion of the plural second element electrodes of the second semiconductor element, (d) an insulation layer coating the major surface of the first semiconductor element and a backside surface of the second semiconductor element, (e) an opening portion formed in the insulation layer and exposing at least a portion of the plural first element electrodes, (f) a wiring layer formed on the insulation layer and electrically connected to the first element electrode exposed in the opening portion, and (g) a plurality of external electrodes formed, as portions of the wiring layer, on the insulation layer and electrically connectable to external equipment.
In an embodiment of the present invention, the first semiconductor element and the second semiconductor element are a semiconductor chip, respectively, and the area of the major surface of the first semiconductor element is greater than the area of the major surface of the second semiconductor element. Further, in an embodiment of the present invention, the first semiconductor element is a semiconductor chip formed in a semiconductor wafer.
It is preferable that at least a portion of the plural external electrodes is formed on the insulation layer located over the backside surface of the second semiconductor element.
In an embodiment of the present invention, the second semiconductor element has on its backside surface at least one external electrode electrically connectable to external equipment.
The semiconductor device of the present invention may further comprise a passivation film formed on the major surface of the first semiconductor element and having opening portions exposing the plural first element electrodes, wherein the insulation layer is formed on the passivation film.
The semiconductor device of the present invention may further comprise metal balls provided on the external electrodes.
The present invention provides a method for the fabrication of a semiconductor device comprising the steps of (a) preparing a first semiconductor element having a major surface on which a plurality of first element electrodes are disposed and a second semiconductor element having a major surface on which a plurality of second element electrodes are disposed, (b) placing the first and second semiconductor elements such that their major surfaces face each other, and thereafter electrically connecting together at least a portion of the plural first element electrodes of the first semiconductor element and at least a portion of the plural second element electrodes of the second semiconductor element by a connection member, (c) forming an insulation layer coating a backside surface of the second semiconductor element and the major surface of the first semiconductor element, (d) forming in the insulation layer an opening portion exposing at least a portion of the plural first element electrodes, and (e) forming on the insulation layer a wiring layer which is electrically connected to the first element electrode exposed in the opening portion, a portion of the wiring layer functioning as an external electrode electrically connectable to external equipment.
It is preferable for the method of the present invention to comprise a step of grinding the backside surface of the second semiconductor element, wherein the step of grinding is performed after the step of electrically connecting together at least the aforesaid portion of the plural first element electrodes and at least the aforesaid portion of the plural second element electrodes.
It is preferable for the method of the present invention to comprise a step of filling an encapsulating resin between the major surfaces of the first and second semiconductor elements facing each other, wherein the step of filling is performed after the step of electrically connecting together at least the aforesaid portion of the plural first element electrodes and at least the aforesaid portion of the plural second element electrodes.
In an embodiment of the present invention, after the step of forming the opening portions in the insulation layer, a step of grinding both the insulation layer and the backside surface of the second semiconductor element and a step of forming another insulation layer on the ground insulation layer and on the ground backside surface of the second semiconductor element, are carried out.
It is preferable for the fabrication method of the present invention to further comprise a step of providing metal balls on the external electrode.
In an embodiment of the present invention, the step of preparing the first and second semiconductor elements is a step of preparing a semiconductor wafer in which a plurality of the first semiconductor elements are formed and preparing a plurality of the second semiconductor elements corresponding to the plural first semiconductor elements formed in the semiconductor wafer, respectively, and after the step of forming the wiring layer a step of dividing the semiconductor wafer is performed such that the plural first semiconductor elements are separated into individual units.
In an embodiment of the present invention, the step of preparing the first and second semiconductor elements is a step of preparing the first and second semiconductor elements which are semiconductor chips.
In the semiconductor device of the present invention, external electrodes are formed on the insulation layer with which the major surface of the first semiconductor element and the backside surface of the second semiconductor element are coated, whereby a two-dimensional arrangement of external electrodes becomes possible to make. This therefore provides a semiconductor device on which a much greater number of external electrodes can be formed, when compared with the conventional semiconductor device using, as an external electrode, an external lead extracted from a lateral surface of the conventional semiconductor device. Further, the semiconductor device of the present invention differs from the conventional semiconductor device in using no lead frame, and in the semiconductor device of the present invention the external electrodes are formed on the insulation layer located on the major surface of the first semiconductor element, whereby the semiconductor device of the present invention can be of the size of the first semiconductor element. The present invention therefore provides a further down-sized semiconductor device than the conventional semiconductor device which is dimensionally constrained by the size of lead frame or the like. If external electrodes are formed on the insulation layer located on the backside surface of the second semiconductor element, this makes it possible to use the entire top surface of the semiconductor device for the layout of external electrodes.
When external electrodes are formed on the backside surface of the second semiconductor element, this guides heat, generated in the second semiconductor element, directly to external equipment (e.g., a wiring substrate) where the heat is released. Therefore, the heat releasabiltiy of the semiconductor device can be improved.
When a passivation film is formed on the major surface of the first semiconductor element, the first semiconductor integrated circuit part, contained in the first semiconductor element, can be protected by the passivation film. When a metal ball is provided on the external electrode, this makes it possible to electrically connecting together the external electrode and the wiring substrate through the metal ball in a simple and quick process. Additionally, the provision of the metal ball on the external electrode makes it possible to widen the distance between the external electrode and the wiring substrate, thereby relaxing thermal stress caused by the difference in linear expansion coefficient between the semiconductor device and the wiring substrate and applied to a joint between the semiconductor device and the wiring substrate.
In the semiconductor device fabrication method of the present invention, the step of forming on the insulating layer the wiring layer, which is electrically connected to the first element electrode and portions of which function as external electrodes, is carried out. Thus, the first element electrode and the external electrode can be connected together electrically without using a wire bonding technique used in the conventional technology. Therefore, the present invention is able to provide formation of finer wiring in comparison with the prior art technology. Further, wiring collectively formable in a semiconductor wafer can be prepared and the length of wiring can be made shorter in comparison with the conventional technology, thereby enabling fabrication of a semiconductor device exhibiting improved electrical characteristics.
The thickness of the semiconductor device can be reduced by grinding of the backside surface of the second semiconductor element. When using a pre-thinned second semiconductor element, its handling is difficult because of possible chip breakage or the like. On the other hand, such handling difficulty can be reduced by subjecting to the backside surface of the second semiconductor element to grinding.
In the case that encapsulating resin is filled between the major surface of the first semiconductor element and the major surface of the second semiconductor element, the strength of joining together these semiconductor elements is enhanced. Moreover, such encapsulating-resin filling prevents formation of voids between the major surface of the first semiconductor element and the major surface of the second semiconductor element, thereby preventing the semiconductor device from undergoing cracking due to expansion of water vapor collected in a void. Therefore, semiconductor devices, which are advantageous in being subjected to testing on water absorption and reflow resistance, can be fabricated.
In the case that both the insulation layer and the backside surface of the second semiconductor chip are ground and another insulation layer is formed on the ground insulation layer and on the ground backside surface of the second semiconductor chip, the planarity of the insulation layer is secured and the planarity of the external electrode is made good. Preparation of a semiconductor wafer in which a plurality of the first semiconductor elements have been formed makes it possible to carry out each of the fabrication steps in the semiconductor wafer state, therefore considerably reducing manufacturing costs.